1. Field of the Invention
The present invention relates generally to digital-to-analog converters, and more particularly, to a digital-to-analog converter using a high-speed single-ended input interface network for coupling digital input signals to a plurality of bit switches within the digital-to-analog converter.
2. Description of the Prior Art
Monolithic digital-to-analog converter circuits are well known in the art and typically include a plurality of bit switches each responsive to a particular bit within the input digital word for selectively steering an associated bit switch current to a summing node at which an analog output current is provided. The current contributed to the analog output current by each of the plurality of bit switches is scaled in a binary weighted fashion in accordance with the binary weighting of the particular bit to which each bit switch is responsive.
In order to maintain the bit switch currents relatively constant over changes in temperature, processing, power supply voltage, etc., it has been common practice in the art to utilize a closed loop amplifier to bias the bit switch current sources. Any variations in bit switch currents are monitored via a reference current source biased by the closed loop amplifier; the current within the reference current source is fed back to an input of the amplifier for readjusting the bias voltage provided by the output of the amplifier in order to maintain the current within the reference current source (and, hence, within the bit switch current sources) constant.
However, the bandwidth of such closed loop amplifiers is typically limited to one Megahertz or less; the operation of the closed loop amplifier is disturbed if relatively high frequency transients are imposed upon the bias voltage, as may occur when one or more of the bit switches undergoes a rapid transition. Due to the inability of such closed loop amplifiers to respond to such high frequency transients, prior art digital-to-analog converters typically utilize a differential input interface network for differentially driving the bit switch and thereby minimizing the amount of voltage shift at the collector of the bit switch current source, and hence, reducing the magnitude of any transients coupled to the current source bias conductor. It is also common practice in the prior art to slow the transition rate of input pulses by adding series resistance and shunt capacitance to the base of the input transistor of the input interface network. Such a differential input network known in the art is disclosed in U.S. Pat. No. 4,056,740 issued to Schoeff.
Although the prior art practice of slowing the transition rate of the input pulse by adding series resistance and shunt capacitance has often been successful in preventing large transients from becoming coupled into the bit switch current source bias voltage, the settling time of such digital-to-analog converters is increased thereby. Furthermore, the differential input interface networks known in the art are constructed from a relatively large number of components and require a relatively large number of metalization runs and crossovers when fabricated.
Accordingly, it is an object of the present invention to provide a digital-to-analog converter which exhibits relatively fast settling time.
It is another object of the present invention to provide a high speed input interface network for use in conjunction with a digital-to-analog converter.
It is still another object of the present invention to provide an input interface network for a monolithic digital-to-analog converter wherein the input interface network exhibits high speed and is relatively easy to fabricate.
These and other objects of the present invention will become more apparent to those skilled in the art as the description thereof proceeds.